Integrated circuits (IC's) and other semiconductor devices are extremely sensitive to high voltages that may be generated by contact with an ESD event. As such, electrostatic discharge (ESD) protection circuitry is essential for integrated circuits. An ESD event commonly results from the discharge of a high voltage potential (typically, several kilovolts) and leads to pulses of high current (several amperes) of a short duration (typically, 100 nanoseconds). An ESD event is generated within an IC, illustratively, by human contact with the leads of the IC or by electrically charged machinery being discharged in other leads of an IC. During installation of integrated circuits into products, these electrostatic discharges may destroy the IC's and thus require expensive repairs on the products, which could have been avoided by providing a mechanism for dissipation of the electrostatic discharge to which the IC may have been subjected.
The ESD problem has been especially pronounced in complementary metal oxide semiconductor (CMOS) field effect transistors. To protect against these over-voltage conditions, silicon controlled rectifiers (SCR) and other protection devices such as the grounded-gate NMOS have been incorporated within the circuitry of the CMOS IC to provide a discharge path for the high current produced by the discharge of the high electrostatic potential. Prior to an ESD event, the SCR is in a nonconductive state. Once the high voltage of an ESD event is encountered, the SCR then changes to a conductive state to shunt the current to ground. The SCR maintains this conductive state until the voltage is discharged to a safe level.
FIG. 1A depicts a schematic diagram of a prior art SCR included within an integrated circuit to provide ESD protection as illustratively provided in U.S. Pat. Nos. 5,465,189 and U.S. Pat. No. 5,502,317. In particular, an illustrative prior art integrated circuit 100 has an SCR protection circuit 101 connected from a pad 148 to ground. The pad 148 is also connected to the protected circuitry of the IC, optionally through a current limiting resistor RL. The SCR protection circuit 101 comprises a trigger device 105 and an SCR 102. The SCR 102 further comprises a NPN transistor T1 131 and a PNP transistor T2 132. In particular, the SCR protection device 101 includes an anode 122, which is connected to the pad 148, and to one side of a resistor RB2 142. The resistor RB2 142 represents the resistance of the N-Well, which is seen at the base of a PNP transistor of the SCR 102, as is discussed in further detail below. Additionally, the anode 122 is coupled to an emitter 108 of a PNP transistor T2 132, which is parallel to the N-Well resistance RB2 142. A first node 134 includes the base of the PNP transistor T2 132, the other side of the resistor RB2 142, and the collector of the NPN transistor T1 131. Additionally, the collector 106 of the PNP transistor T2 132 is connected to a second node 136, which is also connected to the base 106 of the NPN transistor T1 131, and to one side of a resistor RB1 141. The other side of resistor RB1 141 is connected to a third node 124 that is grounded, and which serves as the cathode. Furthermore, the emitter 112 of the NPN transistor T1 131 is also connected to the grounded third node 124.
The triggering device 105 is illustratively a grounded gate NMOS (GGNMOS) transistor, which has its source 127 and gate 126 coupled to ground. Additionally, the drain 129 and source 127 of the GGNMOS transistor 105 are respectively coupled to the collector 110 and the emitter 112 of the NPN transistor T1 131. Furthermore, the gate 126 and source 127 of the GGNMOS transistor are also connected to the grounded third node 124 (i.e., cathode of the SCR).
FIG. 1B depicts a cross-sectional view of a prior art low voltage triggering SCR (LVTSCR) device as depicted in FIG. 1A. Furthermore, FIG. 1B illustratively includes the schematic diagram of the SCR circuit as related to the P and N doped regions of the IC 100. Specifically, the integrated circuit 100 includes a P-type substrate 103 into which an N-Well 104 and P-well 106 are formed adjacent to each other. A junction 107 is formed at the adjoining boundary of the N-Well 104 and the P-well 106.
Within the N-Well 104, a first P+ region 108 is formed. Furthermore, within the P-well 106, a first N+ region 112 and a second P+ region 114 are formed thereupon. In addition, a second N+ region 110 is formed over both the P-well 106 and N-Well 104 regions such that the second N+ region 110 overlaps the junction 107 of the P-well and N-Well regions 106 and 104. The regions denoted P+ an N+ are regions having higher doping levels than the N-Well and P-well regions 104 and 106.
Shallow trench isolation (STI) is used in most state-of-the-art CMOS processing technologies to laterally separate the high-doped regions. Shallow trench isolation is performed prior to forming the high P+ and N+ doped regions. In particular, trenches are etched in specific areas from the silicon surface, and an insulator material (e.g., silicon dioxide (SiO2)) is deposited to fill the trenches. A gate dielectric layer such as silicon dioxide (SiO2) 130 is grown over the parts of the surface exposing bare silicon. A gate electrode material (e.g. poly silicon) is deposited over the entire surface. The gate electrode material and the gate dielectric are structured by a photo-lithographical masking followed by an etching step. After the masking and etching steps, only the photo patterned area of the gate dielectric 130 and the gate electrode 128 remain, as illustrated. Then, the silicon between the STI receives ion implants to form the high-doped P and N regions as discussed above.
Specifically, after performing the STI and creating the high-doped regions, a first STI region 1161 is positioned illustratively to the left of the first P+ doped region 108. Additionally, a second STI region 1162 is positioned between the first P+ region 108 and the second N+ region 110. Furthermore, a third STI region 1163 is positioned between the first N+ region 112 and the second P+ region 114, and a fourth STI region 1164 is positioned to the left of the second P+ region 114.
The gate 126 of the GGNMOS transistor 105 separates the first and second N+ regions 112 and 110. Furthermore, the GGNMOS transistor 105 is used to “trigger”, i.e., turn on the SCR. In particular, the GGNMOS transistor 105 is an N-channel MOS transistor, which includes a drain 129 and source 127, which are respectively formed by the second N+ region 110 and the first N+ region 112. The NMOS-channel is formed at the surface of the P-well region 120 between the first and second N+ regions 112 and 110. Additionally, since the gate 126 is grounded, the P-well region 120 is prevented from forming the NMOS-channel between the first and second N+ regions 112 and 110, thereby preserving the functionality of the SCR's bipolar transistor T1 131.
The NPN transistor T1 131 has its emitter formed by the first N+ region 112, the base formed by the P-well 106, and the collector formed by the N-Well 104, which is electrically in parallel with the second N+ region 110 (NMOS drain 129). The PNP transistor T2 132 has its emitter formed by the first P+ region 108, the base formed by the N-Well 104 and the second N+ region 110, and the collector formed by the P-well 106. It should be noted that the N-Well 104 and the drain region 110 define both the collector of the NPN transistor T1 131 and the base of the PNP transistor T2 132.
The first P+ region 108 is spaced apart from the second N+ region 110. In an instance where the N-Well 104 is optionally connected by an additional N+ region (not shown) to the anode 122, then the N-Well resistance RB2 142 is defined therebetween (For example, an additional N+ region in the N-Well 104). Otherwise, if the N-Well is floating the resistor RB2 142 is not defined (as drawn in phantom in FIG. 1B). As such, the well resistance RB2 142 is the base resistance of the PNP transistor T2 132, and has a resistance value that depends on the N-type material resistivity value. The N-type material includes the level of doping, as well as the length and cross-sectional area of the N-Well 104 (i.e., base). Typically, the resistance RB2 142 is in the range of 500 Ohm to 5000 Ohms, or it is an open if the N-Well is floating (as shown in FIG. 1B). Furthermore, since the second N+ region 110 is coupled to the N-Well 104, the N+ region 110 also functions as part of the base of the PNP transistor T2 132. Likewise, the P-well region 106 forms the base of the NPN transistor T1 131 and also has a substrate resistance RB1 141. Typically, the resistance RB1 141 is in the range of 500 to 5000 Ohms.
The anode 122, cathode 124, and a substrate-tie 125 are respectively coupled to the first P+ region 108, the first N+ region 112, and the second P+ region 114 through silicide layers 118A, 118C, and 118S (collectively silicide layers 118). Furthermore, one skilled in the art will recognize that there are older process technologies that do not have the silicide layer. As such, the anode 122, cathode 124, and substrate-tie 125 are directly connected to the N+ and P+ regions. The silicide layers 118 are formed such that a conductive metal (typically, tungsten or cobalt) is deposited as a very shallow film over the entire IC wafer. A heating step follows and the metal reacts only with the silicon surface to form an alloy of silicon and metal (“silicide”). The other surfaces such as oxides or nitrides do not react with the metal. The non-reacted metal is selectively etched away so that only the silicide layers remain on the silicon. The silicide layers 118 serve as a conductive bonding material respectively between each metal contact 121A, 121C, and 12S (collectively metal contacts 121) of the anode 122, cathode 124, and substrate-tie 125. FIG. 1B depicts a typical implementation where silicide formation is blocked in part of the NMOS 105.
In operation, the protective SCR circuit 102, which comprises the NPN and PNP transistors T1 131 and T2 132, will not conduct current between the anode 122 and the grounded cathode 124. That is, the SCR 102 is turned off, since there is no high voltage (e.g., ESD voltage) applied to the SCR 102, but only the regular signal voltage of the IC. Once an ESD event occurs at the pad 148, a voltage potential appears on the anode 122. Furthermore, the voltage potential created by the ESD event is transferred in part to the N+ region 110 via the N-Well 104. That is, the anode 122, P+ region 108, N-Well region 104, and N+ region 110 are connected in series such that a voltage will form at the N+ region 110.
The N+ region 110 and the P-well 106 form a diode that functions as a triggering mechanism for the SCR 102. In particular, the N+ region 110 and the P-well region 120 act as a diode DR. The diode DR (drawn in phantom) will conduct when the voltage across the diode exceeds the diode reverse breakdown voltage, typically 6-10 volts. That is, once the voltage transferred in part from the ESD event on the N+ region 110 exceeds the diode DR reverse breakdown voltage, an avalanche effect occurs such that holes and electrons are generated in the PN-junction of the diode DR. The holes flow into the P-well regions 120 and 119 of the P-well 106 and to the grounded P+ region 114. The potential in the P-well regions 120 and 119 increases and electrons flow from the N+ region 112 (emitter) mainly into the P-well region 120 and also into the part of the P-well region denoted 119. The flow of minority carriers (electrons) into the P-well region 120 causes the SCR 102 to trigger. Likewise, the electrons generated in the PN-junction of the diode DR will flow into the N-Well 104 and cause the P+ emitter 108 to inject minority carriers (holes) into the N-Well 104.
Specifically, the majority carriers (i.e., holes) generated at the PN-junction of the N+ region 110 and the P-well region 120 recombine in the P-well regions 120 and 119 with the minority carriers (electrons) injected from the N+ region 112 (emitter). As such, the base of the NPN transistor T1 131 draws current, illustratively at the gate G1 in the P-well region 120, which subsequently turns on the NPN transistor T1 131. Furthermore, the collector of the NPN transistor T1 131 is coupled to the base of the PNP transistor T2 132, which turns on the PNP transistor T2 132. The collector current of the NPN transistor T1 131 equals the current gain of T1 131 (β1) times the base current of the transistor T1 131. The current gain β1 is dependent on the geometrical dimensions and the doping levels in the base and emitter of the NPN transistor T1 131. Likewise, a current gain β2 is dependent on the geometrical dimensions and the doping level of the PNP transistor T2 132.
As such, once the NPN transistor T1 131 is turned on, the T1 131 collector provides the base current to the PNP transistor T2 132. Therefore, the base current of the PNP transistor T2 132 is greater than the base current of the NPN transistor T1 131. Moreover, the current gain β2 of the PNP transistor T2 132 is realized as the T2 132 collector current, which is then fed back to the base of the NPN transistor T1 131, thereby amplifying the base current of the NPN transistor T1 131. This amplification of the base currents in the SCR 102 progressively continues to increase in a loop between both transistors T1 131 and T2 132. Therefore, the conduction occurring in a turned on SCR is also called a “regenerative process”.
The SCR 102 becomes highly conductive and sustains the current flow with a very small voltage drop between the anode and cathode (typically, 1-2V). Accordingly, once the SCR 102 is turned on, the current from the ESD event passes from anode 122 to the grounded cathode 124. As such, the SCR 102 protects the remaining portion of the IC circuitry 100. Once the ESD event has been discharged from the anode 122 to the cathode 124, the SCR 102 turns off because it cannot sustain its regenerative conduction mode.
It is critical to discharge the ESD event as quickly as possible to prevent damage to the circuitry of the IC, as well as to the protective SCR itself. In the above prior art LVTSCR, the NMOS transistor 105 is integrated within the SCR 102. The N+ region diffusion 110, which is inserted as an integrated trigger means, is disadvantageous due to the excessive base widths of the NPN transistor T1 131 and the PNP transistor T2 132. Therefore, the large lateral T1 and T2 transistor dimensions, due to the insertion of the N+ diffusion and the high recombination of charge carriers, results in slow SCR triggering. In particular, the N+ region 110 (“trigger diffusion region”), which is also part of the base of the PNP transistor T2 132, deteriorates the current gain of this part of T2 132. That is, since the N-Well region 104 has the higher doped N+ region 110 disposed therein, the overall current gain β2 of the transistor T2 132 is reduced, which may impede (e.g., delay or prevent) the SCR 102 from triggering during an ESD event. Therefore, there is a need in the art for a fast triggering SCR protection device having a reliable and controllable triggering mechanism.
Circuit designers have often found it advantageous to provide circuitry to allow power supply lines to go into a power-down mode, illustratively for power saving purposes. Power-down mode means that one or more of the different supplies can connect to ground, while other supply lines of the IC remain powered. Therefore, portions of IC circuit that are not currently utilized for the functional aspects of the IC may be temporarily powered down to save power, and then the lines are powered up as required.
FIGS. 9A and 9B depict two prior art circuits illustratively providing power line to power line coupling for ESD protection between the power lines. Referring to FIG. 9A, first and second power lines 9021 and 9022 are coupled by “anti-parallel” (i.e., anti-parallel) diodes 9061 and 9062. The first and second power lines 9021 and 9022 illustratively have a voltage potential above ground 904 during normal circuit operation. Since the anti-parallel diodes 9061 and 9062 are coupled in parallel between the first and second power lines 9021 and 9022, if one of the power lines 902 goes to ground 904, then one of the diodes 906 will become forward-biased, conduct, and essentially shunt the other supply line also to ground 904. For example, if the first power line 902, is powered down to ground 904, the exemplary diode 9062 will become forward biased, conduct, and effectively shunt the current from the second power line 9022 to ground 904. Accordingly, the anti-parallel diodes 906 between the power lines 902, as illustratively shown in FIG. 9A, do not provide a solution that is compatible with a “power down mode”. Such a “power down mode” is present on integrated circuits when parts of the circuitry are powered down for reasons of limiting energy consumption.
FIG. 9B depicts an NMOS device 908 coupled between two power lines 9021 and 9022 providing ESD protection that is compatible with a power down mode during normal circuit operation. In particular, a source of the NMOS device 908 is illustratively coupled to a first power line 9021, while a drain of the NMOS device 908 is coupled to second power line 9022. Furthermore, the gate and P-substrate of the NMOS device 908 are coupled to ground 904. The N+ regions disposed in the P-substrate form the source and drain regions of the NMOS device 908. It is noted that the drain and source regions of the NMOS device 908 are symmetrical and exchangeable depending on the applied voltage polarity.
Furthermore, N+ regions and the P-substrate collectively form a parasitic bipolar transistor, where the N+ to P-substrate junctions form reversed biased diodes 910, as illustratively shown as diodes 9101 and 9102 (drawn in phantom). In an instance where one of the power lines is grounded, the other power line will not be shunted to ground 904 because of the reverse biased diode 910 formed by the corresponding N+ region and P-substrate.
Specifically, if one of the power lines 902 is powered down to ground 904, while the other power line is still powered up, the lateral parasitic NPN transistor of the symmetrical NMOS device 908 will always have one of the N+ to P-substrate junctions reverse biased. For example, if the first power line 9021 is powered down to ground 904, while the second power line 9022 is still powered up, the reverse bias diode 9011 formed by the lateral parasitic NPN transistor of the NMOS device 908, will prevent the first power line 9021 from shunting current to ground 904. It is noted that since the P-substrate and the gate of the NMOS device 908 are connected to ground 904, the NMOS current between the drain and the source is shut off.
Although the NMOS-based ESD protection device 908 of FIG. 9B is power down compliant, the NMOS device 908 has poor ESD voltage clamping characteristics. Furthermore, the NMOS ESD protection device 908 is not area-efficient, and therefore encumbers manufacturing techniques that attempt to further reduce the size of the ICs. Therefore, there is a need in the art for an ESD protection circuit that provides improved ESD voltage clamping between power lines, wherein the power lines are allowed to operate in a power down mode of operation, while having a very high ESD protection performance and high area-efficiency.